Xiang Pan
About Me:
I received my Ph.D. from Department of Computer Science and Engineering of The Ohio State University in 2017. My research focused on Software/Hardware Co-Design for Processor Power-Efficiency and Security. I was a member of Computer Architecture Research Lab working with Prof. Radu Teodorescu. Currently I'm working as a Software Engineer at Apple AI/ML on building Siri search backend systems.
Education:
Ph.D. in Computer Science, The Ohio State University, 2010 ~ 2017
B.E. in Computer Science, Beijing University of Posts and Telecommunications, 2006 ~ 2010
Industry Experience:
Software Engineer @ Apple (Cupertino, CA), August 2020 ~ Present
Software Engineer @ Uber (San Francisco, CA), June 2018 ~ August 2020
Software Engineer @ Qualcomm (Austin, TX), April 2017 ~ June 2018
Software Engineering Intern @ Samsung Austin R&D Center (Austin, TX), May 2015 ~ August 2015
Research Intern @ Hewlett-Packard Laboratories (Palo Alto, CA), May 2014 ~ August 2014
Software Engineering Intern @ Hewlett-Packard Enterprise (Boise, ID), May 2013 ~ August 2013
Research Intern @ Tsinghua University Microprocessor and SoC Technology R&D Center (Beijing, China), June 2009 ~ June 2010
Dissertation:
Xiang Pan, Designing Future Low-Power and Secure Processors with Non-Volatile Memory, Ph.D. Thesis, April 2017 (slides)
Advisor: Radu Teodorescu Committee Members: Feng Qin, Christopher Stewart, Yinqian Zhang
Publications:
Xiang Pan, Anys Bacha, Spencer Rudolph, Li Zhou,Yinqian Zhang, Radu Teodorescu, NVCool: When Non-Volatile Caches Meet Cold Boot Attacks, The 36th IEEE International Conference on Computer Design (ICCD), October 2018 (slides)
Xiang Pan, Anys Bacha, Radu Teodorescu, Respin: Rethinking Near-Threshold Multiprocessor Design with Non-Volatile Memory, The 31st IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 2017 (slides)
Xiang Pan and Radu Teodorescu, NVSleep: Using Non-Volatile Memory to Enable Fast Sleep/Wakeup of Idle Cores, The 32nd IEEE International Conference on Computer Design (ICCD), October 2014 (slides)
Xiang Pan and Radu Teodorescu, Using STT-RAM to Enable Energy-Efficient Near-Threshold Chip Multiprocessors, The 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT), August 2014 (short paper) (slides, poster)
Timothy Miller, Renji Thomas, Xiang Pan, Radu Teodorescu, VRSync: Characterizing and Eliminating Synchronization-Induced Voltage Emergencies in Many-core Processors, The 39th International Symposium on Computer Architecture (ISCA), June 2012
Timothy Miller, Xiang Pan, Renji Thomas, Naser Sedaghati, Radu Teodorescu, Booster: Reactive Core Acceleration for Mitigating the Effects of Process Variation and Application Imbalance in Low-Voltage Chips, The 18th International Symposium on High-Performance Computer Architecture (HPCA), February 2012
Contact Information:
Email:
panxiang.bupt AT gmail DOT com
Academic Genealogy:
Nathaniel Bowditch, M.A. 1802 (Honorary), Harvard
Benjamin Peirce, A.B. 1829, Harvard
Joseph Lovering, A.B. 1833, Harvard
John Trowbridge, S.D. 1873, Harvard
Wallace Sabine, A.M. 1888, Harvard
Percy Bridgman, Ph.D. 1908, Harvard
John Slater, Ph.D. 1923, Harvard
Samuel Silver, Ph.D. 1940, MIT
Gedaliah Held, Ph.D. 1954, University of California, Berkeley
Akira Ishimaru, Ph.D. 1958, University of Washington
Dick Kieburtz, Ph.D. 1961, University of Washington
John Hennessy, Ph.D. 1977, SUNY Stony Brook
Josep Torrellas, Ph.D. 1992, Stanford
Radu Teodorescu, Ph.D. 2008, University of Illinois, Urbana-Champaign
Xiang Pan, Ph.D. 2017, The Ohio State University
Last Updated: August 2020